High ESD stress sustaining ESD protection circuit

ABSTRACT

An ESD protection circuit suitable for application to an IC. The ESD protection circuit includes a primary discharging component and an ESD detection circuit. The primary discharging component has a control end. The ESD detection circuit comprises a capacitor, a first resistor and a second resistor. The capacitor and the first resistor are formed in series and coupled between the control and a first pad of the IC. The second resistor is coupled between a second pad of the IC and the control end. The primary discharging component is closed during normal power operations, and triggered by the ESD detection circuit during an ESD event. During an ESD event, the capacitance becomes short-circuited, leaving voltages at the control end dominated by a resistive voltage divider formed by the first resistor and the second resistor. The ESD detection circuit provides a suitable voltage to the control end allowing the primary discharging component to release the optimum amount of ESD stress.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates in general to an electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to an ESD protection circuit suitable for application in an integrated circuit (IC).

[0003] 2. Description of the Related Art

[0004]FIG. 1 shows a conventional ESD protection circuit of an IC. The ESD protection circuit 10 has an NMOS N_(ESD) coupled between a pad 12 and a power line V_(SS). A RC coupling circuit is formed by a capacitor C and a resistor R in the circuit. When an ESD voltage, positive with respect to the power line V_(SS) occurs at the pad 12, a positive voltage is coupled to a gate of the NMOS N_(ESD) enhancing the triggering rate of the NMOS N_(ESD). Generally, an IC chip with ESD protection circuits must sustains more than the minimum human-body-mode (HBM) ESD stress, 2 k volts. However, when the gate of the NMOS N_(ESD) is over- or under-stressed, ESD protection of ICs provided by the ESD protection circuit in FIG. 1 is compromised. FIG. 2 shows a fixed voltage applied to the gate of the NMOS N_(ESD) in FIG. 1. An experimental result of voltages at the gate of the NMOS N_(ESD) against the highest voltage N_(ESD) can sustain is shown in FIG. 3. Voltages applied to the gate of the NMOS N_(ESD) allow a triggering voltage of the NMOS N_(ESD) to decreaseer. As shown in FIG. 3, when bias voltages at the gate of the NOS N_(ESD) is small and is increased, ESD stress sustainable by the NMOS N_(ESD) increases. Nevertheless, when bias voltages at the gate of the NMOS N_(ESD) passes an optimized point and is overly increased, large ESD current crossing a thin channel under the NMOS N_(ESD) easily damages the NOS N_(ESD) and causes ESD level sustained by the NMOS N_(ESD) to drop. ESD protection provided by the circuit in FIG. 2 is optimized by bringing a bias voltage at the gate of the NMOS N_(ESD) to a specified amplitude, such as V_(Gopt) in FIG. 3. Therefore, it has become an object for circuit designers to bring bias voltages at the gate of the NMOS N_(ESD) in FIG. 1 to the specified amplitude V_(Gopt) during an ESD event.

[0005] The ESD protection circuit in FIG. 1 may be unreliable during an ESD event. Capacitances of parasitic capacitors, such as C_(gd) and C_(gs), formed in the NMOS N_(ESD) sway during different manufacturing processes. Voltages coupled from ESD stress at the pad 12 to the gate of the NMOS N_(ESD) are undoubtedly affected by the changing capacitances. In addition, ESD stresses occur on the pad 12 at different rates. Therefore, voltages coupled to the gate of the NMOS N_(ESD) are unpredictable, resulting in unreliable performance. For instance, the circuit in FIG. 1 might have sustained a HBM ESD stress of 5 kv, but fails to sustain a HBM ESD stress of 2 kv. Voltages at the gate of the NMOS N_(ESD) in the circuit of FIG. 1 are thus hard to control and are unpredictable during a manufacturing process.

SUMMARY OF THE INVENTION

[0006] An object of the present invention is to provide an ESD protection circuit having an ESD detection circuit. The ESD detection circuit provides an appropriate gate voltage to a MOS optimizing ESD protection provided by the ESD protection circuit.

[0007] In accordance with the object described, the present invention provides an ESD protection circuit, suitable for application in an IC. The ESD protection circuit comprises a primary discharging component and an ESD detection circuit. The primary discharging component has a control end. The ESD detection circuit comprises a capacitor, a first resistor, and a second resistor. The capacitor and the first resistor are formed in series and coupled between the control and a first pad of the IC. The second resistor is coupled between a second pad of the IC and the control end. The primary discharging component is closed during normal power operations, and triggered by the ESD detection circuit during an ESD event.

[0008] The combination of the first pad and the second pad may be a power line and a pad, or two power lines. The primary discharging component can be an NMOS or a PMOS.

[0009] The ESD protection circuit of the present invention is suitable for application to a primary or secondary ESD protection circuit of an I/O pad.

[0010] Capacitance of the capacitor must be properly selected. The capacitance, on one hand, should be low enough during normal power operations that voltages coupled to the control end are not too large to trigger the discharging component, and on the other hand should be high enough that the capacitance resembles a short circuit during an ESD event.

[0011] During an ESD event, the ends of the capacitance are short-circuited, leaving voltages at the control end dominated by a resistive voltage divider formed by the first resistor and the second resistor. Control of voltages at the control end allows ESD protection provided by the primary discharging component to be optimized.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention can be more fully understood by reading the subsequent detailed description in conjunction with the examples and references made to the accompanying drawings, wherein:

[0013]FIG. 1 is a conventional ESD protection circuit in an IC;

[0014]FIG. 2 is a schematic diagram showing a fixed voltage applied on the gate of the NMOS N_(ESD) in FIG. 1;

[0015]FIG. 3 is a diagram showing gate voltages against ESD stress sustained;

[0016]FIG. 4 is an ESD protection circuit of the present invention having an NMOS;

[0017]FIG. 5 is an ESD protection circuit of the present invention having a PMOS;

[0018]FIG. 6 is a diagram of voltages against current when the bias voltage at the gate of the NMOS N_(ESD) is V_(Gopt);

[0019]FIG. 7 is a two stage ESD protection circuit of the present invention implemented by ESD protection circuits;

[0020]FIG. 8 is a power-rail ESD clamping circuit implented by an NMOS in accordance with the present invention; and

[0021]FIG. 9 is a power-line ESD clamping circuit implemented by a PMOS in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0022]FIG. 4 is an ESD protection circuit of the present invention having an NMOS. The ESD protection circuit 20 in FIG. 4 is coupled between an anode and a cathode and comprises an NMOS N_(ESD) and an ESD detection circuit 22. The ESD detection circuit 22 distinguishes an ESD event from normal operations. The NMOS N_(ESD) is closed during normal power operations and turned on during an ESD event. The ESD detection circuit 22 has a capacitor C_(n), a resistor R_(n1), and a resistor R_(n2). The capacitor C_(n) and the resistor R_(n1) are coupled between the anode and a gate of the NMOS N_(ESD) with flexible sequence. The resistor R_(n2) is coupled between the gate of the NMOS N_(ESD) and the cathode.

[0023] The anode and the cathode are respectively coupled to two pads, such as I/O pads or power lines. The anode is coupled to a high voltage with respect to the cathode during normal power operations.

[0024] The capacitance of the capacitor C_(n), on one hand, has to be low enough so that voltages coupled to a gate of the NMOS N_(ESD) are not too high to trigger the NMOS N_(ESD) during normal power operations (having low operational frequency), and on the other hand, has large enough so that the capacitor C_(n) resembles a state of short circuit with respect to the resistors R_(n1) and R_(n2) during an ESD event (having high operational frequency). This is realized using the impedance (=1/(2*pi*C_(n)*f)) of the capacitor C_(n) fluctuating with operational frequencies f.

[0025] During normal power operations, the gate of the NMOS N_(ESD) is coupled to the cathode having a low voltage through the resistor R_(n2) so that the NMOS N_(ESD) is turned off to avoid current leakage.

[0026] When a positive ESD stress with respect to the cathode occurs at the anode, voltages (V_(G)) at the gate of the NMOS N_(ESD) can be represented with an equation (1):

V _(G) =V _(A−C) *R _(n2)/(R _(n1) +R _(n2)+1/(2*pi*C _(n) *f))  (1)

[0027] V_(A−C) represents the voltage difference between the anode and the cathode. The capacitor C_(n) resembles a short circuit with respect to the resistors R_(n1) and R_(n2) (R_(n1), R_(n2)>>1/(2*pi*C_(n)*f)). The equation (1) can thus be simplified to an equation (2) as follows:

V _(G) =V _(A−C) *R _(n2)/(R _(n1) +R _(n2))  (2)

[0028] As shown in FIG. 3, the optimum amount of ESD stress sustainable by the ESD protection circuit 20 is recorded when the ESD protection circuit 20 is triggered at a bias voltage of V_(Gopt) at the gate of the NMOS N_(ESD). FIG. 6 shows a diagram of voltages against current for the protection circuit 20 when a bias voltage at the gate of the NMOS N_(ESD) in FIG. 4 is V_(Gopt). Once voltage at the anode reaches V_(break) _(—) _(opt) in a condition that the bias voltage at the gate of the NMOS N_(ESD) is V_(Gopt), snapback occurs at the NMOS N_(ESD) to release the ESD current. Namely, when the bias voltage at the gate of the NMOS N_(ESD) is V_(Gopt), the maximum voltage at the anode is V_(break) _(—) _(opt). Such a character is applied into the equation (2) to optimize the ESD protection circuit 20 in FIG. 4 and result in the following equation:

V _(Gopt) =V _(break) _(—) _(opt) *R _(n2)/(R _(n1) +R _(n2))  (3)

[0029] Once such a relationship between the resistors R_(n1) and R_(n2-) is acquired, the NMOS N_(ESD) is triggered when the voltage across the anode and the cathode reaches V_(break) _(—) _(opt) and the voltage at the gate of the NMOS N_(ESD) is at V_(Gopt). The ESD stress is released and the optimum ESD protection is performed.

[0030] Similarly, the ESD protection circuit in the present invention can be implemented by a PMOS in FIG. 5. As in FIG. 4, connections of components in FIG. 5 are displayed without further descriptions.

[0031]FIG. 7 is a schematic diagram of a two-stage ESD protection circuit implemented by ESD protection circuits of the present invention. The two-stage ESD protection circuit comprises a primary ESD protection circuit 24, a resistor R_(buff) and a secondary ESD protection circuit 26. An ESD protection circuit of the present invention is formed in the primary ESD protection circuit 24 by an NMOS N_(ESD1), a resistor R_(n1), a resistor R_(n2) and a capacitor C_(n1) between a pad 30 and a power line VSS. Similar structures are formed between the pad 30 and a power line VDD, an internal circuit 28 and the power line VDD, and the internal circuit 28 and the power line VSS. The secondary ESD protection circuit 26 is used to clamp voltages received by the internal circuit 28. The primary ESD protection circuit 24 is used to release most of the ESD stress. Therefore, a PMMOS P_(ESD2) and an NMOS N_(ESD2) in the secondary ESD protection circuit 26 are relatively small in comparison with a PMOS P_(ESD1) and the NMOS N_(ESD1) in the primary ESD protection circuit 24.

[0032] The ESD protection circuit of the present invention is also suitable for application to ESD clamping circuits formed between power lines, as shown in FIGS. 8 and 9. An ESD clamping circuit between power lines implemented by an NMOS in accordance with the present invention is shown in FIG. 8. An ESD clamping circuit between power lines implemented by a PMOS in accordance with the present invention is shown in FIG. 9.

[0033] Voltages at gates in a conventional ESD protection circuit are difficult to maintain at an appropriate level. In comparison, the ESD protection circuit of the present invention formed by a short-circuited capacitor and a resistive voltage divider provides an appropriate voltage for NMOSs or PMOSs to release the optimum amount of ESD stress.

[0034] Finally, while the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. 

What is claimed is:
 1. An electrostatic discharge (ESD) protection circuit, suitable for application to an integrated circuit (IC), the ESD protection circuit comprising: a primary discharging component, having a control end; and an ESD detection circuit, comprising: a capacitor and a first resistor formed in series, and coupled between the control end and a first pad of the IC; and a second resistor, coupled between the control end and a second pad of the IC; wherein the primary discharging component is closed during normal power operations, and triggered by the ESD detection circuit during an ESD event.
 2. The ESD protection circuit in claim 1, wherein the primary discharging component is an N-type metal-oxide-semiconductor, MOS, coupled between the first pad and the second pad.
 3. The ESD protection circuit in claim 2, wherein a first operating voltage of the first pad is higher than a second operating voltage of the second pad during normal power operations.
 4. The ESD protection circuit in claim 2, wherein the first pad is an input/output (I/O) pad, and the second pad is a power line V_(SS).
 5. The ESD protection circuit in claim 2, wherein the first pad is a first power line V_(DD) and the second pad is a second power line V_(SS).
 6. The ESD protection circuit in claim 1, wherein the primary discharging component is a PMOS coupled between the first pad and the second pad.
 7. The ESD protection circuit in claim 6, wherein a first operating voltage of the first pad is lower than a second operating voltage of the second pad during normal power operations.
 8. The ESD protection circuit in claim 6, wherein the first pad is an input/output (I/O) pad, and the second pad is a power line V_(DD).
 9. The ESD protection circuit in claim 6, wherein the first pad is a power line V_(SS) and the second pad is a power line V_(DD).
 10. The ESD protection circuit in claim 1, wherein the ESD protection circuit is a primary ESD protection circuit of an I/O pad
 11. The ESD protection circuit in claim 1, wherein the ESD protection circuit is a secondary ESD protection circuit of an I/O pad, and is coupled to the first pad or the second pad through a buffering resistor.
 12. An ESD protection circuit, coupled between a first pad and a second pad of an IC, comprising: a primary discharging component, coupled between the first pad and the second pad, having a control end; and an ESD detection circuit, coupled to the first pad, the second pad and the control end, and having a resistive voltage divider comprising at least a first resistor and a second resistor coupled in series; wherein during normal power operations, the primary discharging component is closed by the resistive voltage divider, and during an ESD event, the primary discharging component is triggered by the resistive voltage divider to release ESD current during an ESD event.
 13. The ESD protection circuit in claim 12, wherein the ESD protection circuit comprises a capacitor for distinguishing an ESD event from normal power operations.
 14. The ESD protection circuit in claim 13, wherein the first resistor and the capacitor are coupled between the first pad and the control end, and the second resistor is coupled between the control end and the second pad.
 15. The ESD protection circuit in claim 12, wherein the primary discharging component is an NMOS.
 16. The ESD protection circuit in claim 15, wherein, during normal power operations, a first operating voltage of the first pad is higher than a second operating voltage of the second pad.
 17. The ESD protection circuit in claim 12, wherein the primary discharging component is a PMOS.
 18. The ESD protection circuit in claim 17, wherein during normal power operations, a first operating voltage of the first pad is lower than a second operating voltage of the second pad. 